The present invention relates to very large scale integrated circuit (VLSI) semiconductor manufacturing processes, and more particularly to methods for achieving tapered side-wall profiles in device surface layers via plasma etching processes.
isotropic etching is typically performed by wet chemical etching. The openings formed by isotropic etching typically are characterized by large undercut regions. Anisotropic etching is typically performed by dry plasma etching, forming an opening with vertical side-walls. The anisotropic plasma etching technique is in widespread use today to etch contact and via openings, for example.
Poor metal step coverage, especially over the contact or via holes formed by plasma etching in VLSI circuit chips, is a serious problem for circuit yield. The problem gets worse as the circuit dimensions get smaller.
As dry etching becomes one of the mainstream techniques in the VLSI technology, the problem of high contact resistance resulting from dry etching becomes a more significant factor in circuit yields. As is well known, the "metal 1" contact layer is the first metal layer formed on the wafer. The second metal layer or "metal 2" layer is formed over the metal 1 layer and an intervening insulator layer. High contact resistance may result in contacts between the metal 1 and metal 2 layers through via holes formed in the intervening insulator layer and in contacts between the metal 1 layer and polycrystalline silicon ("poly") or active areas which are formed through contact holes. The high contact resistance typically results from the steep side-walls of the contact or via holes which result from dry etching techniques used to form the contact or via holes.
To applicant's knowledge, there are two general techniques of solving the problem of high contact resistance associated with dry etching techniques. The first technique is to employ contact and via plugs; the second technique is to employ side-wall profile tapering of the contact and via holes. The present invention comprises an improvement to the second technique.
In general, applicants understand that the typical technique employed to achieve the tapered side-wall profile involves adding photoresist erosion gases such as oxygen during the plasma etching process. However, use of photoresist erosion gates exacerbates the problem of pinhole formation, and depends heavily on the uncontrollable photoresist flow step prior to plasma etching. Furthermore, the corner of the contact or via hole is not rounded when photoresist erosion gases are added during the plasma etch.
It is therefore an object of the invention to provide a process for side-wall tapering of contact and via holes in VLSI circuit chip wafers which results in virtually pinhole-free step metalization and smoothly tapered side-walls which are reproducible and profile controllable.
Another object of the present invention is to provide an improved metal contact process for the fabrication of VLSI circuits.